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楼主 作者:水木清华 发表时间:2018/9/10 11:11:14 编 辑 | |
公司简介: Magic-Semi(上海实真微电子有限公司)是一家致力于集成电路设计服务和咨询 的高科技企业。Magic-Semi对业界主流EDA厂商工具有着丰富的引用经验,合作项 目设计多家foundry厂商的先进工艺。公司拥有成熟的设计团队,以及优秀的设计 工程师人才,具备丰富的后端设计经验。为员工及实习生提供系统、专业的数字 集成电路后端设计培训。 公司网址: http://www.magic-semi.com 1. 实习生职位实习内容: 独立显卡项目后端设计(FloorPlan、Place、CTS、route、ECO、Timing Analysis 等)。项目均采用TSMC/GF 14nm/10nm 工艺。有机会接触到先进的独立显卡技术 。需要基于实习内容写论文者,公司安排资深工程师进行指导。 实习要求: 1. 集成电路设计、微电子、物理、嵌入式、计算机等相关专业 2. 在读研究生(研一研二均可) 3. 对数字集成电路物理设计有浓厚兴趣 4. 英语四级及以上(英文办公环境) 实习时间:至少半年(一定与导师协商好) 工作地点:上海 简历投递方式: 请有意者发简历(以“学校+专业名+姓名+可实习时间”为主题)到 hr@magic-semi.com 2.应届生 Magic-semi JD for NCG Magic-semi is a new startup design servicecompany specialized in backend training, consulting and design service. In magic-semi, design experters with rich experience in advancetechnology nodes from 40nm to 14nm and can deliver complete solutionfrom netlist to GDSII. Magic-semi has good relationship with IC leadingcompany and enables our customer to achieve success in a more efficient,reliable and cost-effective way. Job Title: Intern/NCG RESPONSIBILITES: 1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute. 2. Work with Front-end designers to optimize timing/area/powerof the design implementation and perform static timing analysis. 3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS). 4. Static Timing analysis (Prime Time or ETS)and setup/hold fix. Requirements: 1. CS/EE or background in areas related todigital or analog chip design 2. Be familiar with IC backend flow. 3. Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus. 4. Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus. 5. Experience and knowledge about FE design(RTL code, flow) and verification is a plus. 6. Good analytical and debugging skills. Send your CV to hr@magic-semi.com if you are interested. 3. 高级工程师 Magic-semi JD forSenior Engineer Magic-semi is a new startup design servicecompany specialized in backend training, consulting and design service. In magic-semi, design experters with rich experience in advancetechnology nodes from 40nm to 14nm and can deliver complete solutionfrom netlist to GDSII. Magic-semi has good relationship with IC leadingcompany and enables our customer to achieve success in a more efficient,reliable and cost-effective way. Job Title: Senior Engineer RESPONSIBILITES: 1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute. 2. Work with Front-end designers to optimize timing/area/powerof the design implementation and perform static timing analysis. 3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS). 4. Static Timing analysis (Prime Time or ETS)and setup/hold fix. Requirements: 1. CS/EE or background in areas related todigital or analog chip design 2. 3 year+ work experience. 3. experience in floorplan, place, cts,route, timing ,pv and power analysis and so on. 4. Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus. 5. Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus. 6. Experience and knowledge about FE design(RTL code, flow) and verification is a plus. 7. Good analytical and debugging skills. Send your CV to hr@magic-semi.com if you are interested. 4. leader Magic-semi JD forLeader Engineer Magic-semi is a new startup design servicecompany specialized in backend training, consulting and design service. In magic-semi, design experters with rich experience in advancetechnology nodes from 40nm to 14nm and can deliver complete solutionfrom netlist to GDSII. Magic-semi has good relationship with IC leadingcompany and enables our customer to achieve success in a more efficient,reliable and cost-effective way. Job Title: Leader Engineer RESPONSIBILITES: 1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute. 2. Work with Front-end designers to optimize timing/area/powerof the design implementation and perform static timing analysis. 3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS). 4. Static Timing analysis (Prime Time or ETS)and setup/hold fix. Requirements: 1. CS/EE or background in areas related todigital or analog chip design 2. 7 year+ work experience for IC backend. 3. Experience in floorplan, place, cts,route, timing ,pv and power analysis and so on. 4. Have experience for project management. 5. Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus. 6. Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus. 7. Experience and knowledge about FE design(RTL code, flow) and verification is a plus. 8. Good analytical and debugging skills. 9. Self-motivated and good team player. Send your CV to hr@magic-semi.com if you are interested. |
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